Dynamic random access memories (dynamic RAM or DRAM) used in computer systems require a very complex set of control signals in order to successfully read data out of or write data into the RAM. For example, the Texas Instruments TMS 4464, a 65,536 word by four bit dynamic RAM, requires a row address strobe, column address strobe and write and read enable signals. These signals must be generated so that they are properly timed not only with respect to each other but with respect to the address and data signals also being applied to the RAM.
Such standard dynamic RAM's use a multiplexed address scheme to reduce the pin count of the integrated circuit. The multiplexed addresses correspond to the internal memory cell array configuration of rows and columns, i.e., a row address enables a row of memory elements in the memory cell array and the column address accesses the particular cell in the row that is in the addressed column. The addressing may be further complicated in custom memory applications where not only are the row and column addresses multiplexed together but they are time multiplexed onto a single bus along with the data to further reduce the pin count. With these custom devices, additional control signals must be provided for the off chip multiplexing of the address and data signals.
The timing of the control signals involved in the memory cycle are influenced by the structure of the memory array and the address and logic. As a result, generating the necessary control signals for a dynamic RAM is rather complex, particularly when one is attempting to operate the RAM as close to its optimal specified timing as possible. In addition, it is desirable to allow the control signal timing to be changed easily to account for changes in the RAM specifications or the redesign of the computer system that results in changes to the timing requirements of the memory subsystem.
Conventional delay lines have been used to generate various control signals as is shown in U.S. Pat. No. 4,494,021 issued to A. G. Bell et al. In these delay lines, a common clock signal is applied to every stage so that each stage is clocked in unison. Therefore, the minimum time period between the generation of different control signals is one cycle of the input clock. In certain applications this input clock may operate at 25 MHz resulting in a 40 nanosecond clock period. Therefore at best, a different control signal could be produced only every 40 nanoseconds from a conventional tapped delay line. For optimal access to some RAM's, a 20 nanosecond timing period is desired. The only way of achieving this with a conventional tapped delay line is to double the clock frequency to 50 MHz which may not be practical, especially if the delay line is fabricated using CMOS technology.
Another method for generating these RAM control signals would be a finite state machine consisting of a programmed logic array (PLA) and a latch. By changing the PLA, the timing of the circuit could be altered. A problem with this approach develops when the memory control signal generator is fabricated on a CMOS integrated circuit which limits the maximum clock frequency to approximately 25 MHz. A PLA based state machine would be too slow to generate the precise 20 nanosecond timing.